Low-Power, All Digital Phase-Locked Loop with a Wide-Range, High Resolution TDC
نویسندگان
چکیده
منابع مشابه
A Frequency Synthesis of All Digital Phase Locked Loop
All Digital Phase locked loops (ADPLL) plays a major role in System on Chips (SoC). Many EDA tools are used to design such complicated ADPLLs. It operates on two modes such as frequency acquisition mode and phase acquisition mode. Frequency acquisition mode is faster compared to Phase acquisition, hence frequency synthesis is performed. The CMOS technology is used to design such a complex desig...
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In this paper, a high speed delay-locked loop (DLL) architecture ispresented which can be employed in high frequency applications. In order to design the new architecture, a new mixed structure is presented for phase detector (PD) and charge pump (CP) which canbe triggered by double edges of the input signals. In addition, the blind zone is removed due to the elimination of reset signal. Theref...
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Phase error dynamics of a conventional second order Digital Phase Locked Loop (DPLL) and that of a newly proposed modified second order DPLL (MSODPLL) have been studied using digital computers. Ranges of initial conditions leading to the phase locking condition were determined from computer simulation of both conventional and modified second order DPLL. Lyapunov exponents were also examined, fo...
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ژورنال
عنوان ژورنال: ETRI Journal
سال: 2011
ISSN: 1225-6463
DOI: 10.4218/etrij.11.0110.0295